Conventionally, research and development have been done on Network-on-Chip (NoC) which is an approach for solving the difficulty in designing bus that allows expansion in the scale of the semiconductor device, using the network technology between the processors or the bus masters. Instead of conventional crossbar switch that intensively controls the processors and bus masters, the bus is networked by mutually connecting the chips and the bus masters through a NoC router (router). This facilitates adding or deleting functions in the semiconductor system, and allows the traffic to be dispersed. However, the control is dispersed as well, which makes the control more complex. In order to address this problem, implementing the scheme which automatically optimizes the traffic control increases the efficiency in bus to the maximum extent. This lowers the operation clock of the bus and reduces unnecessary processing, thereby attempting to lower power consumption. Furthermore, autonomous and harmonious increase of the use efficiency of the bus by the semiconductor device itself allows reducing the workload on the semiconductor device developer when developing the semiconductor device. Challenges in controlling the traffic in the bus stems from the change in traffic is due to switch in content to be processed, user operations, and processing methods. In order to avoid the challenge due to the traffic change, the lowest value is used in simulation for the current semiconductor devices. This lowers the use efficiency of the bus, making it difficult to reduce the consumption power of the semiconductor device. In addition, estimating the lowest value is not an easy task. This problem is even more serious in the NoC with the dispersed bus. The present invention reduces the consumption power and reduces the workload on the semiconductor device developer at the time of development, by automatically optimizing the traffic control of the bus, lowering the operation clock of the bus, and newly providing a function for reducing the unnecessary process. Dispersing the bus is one of the methods for increasing the use efficiency of the bus. This creates multiple paths for the destination bus master (the components of the semiconductor device such as, Digital Signal Processor (DSP), processor, IO, memory, and others). The present invention is for a method for selecting a high transmission quality bus, and switching the paths for optimizing the traffic control.
Patent Literature 1 discloses a technology for continuing the transmission when a transmission error occurs and there is no response to the error by newly selecting a path.
[Citation List]
[Patent Literature]
    [Patent Literature 1] Japanese patent No. 3816531